“This article will discuss the details of interfacing a basic 16x2 LCD module with an FPGA.
In the previous article, we examined the building blocks needed for interfacing an FPGA with a common 16x2 LCD module. We saw that the main building blocks are ROM, some DFFs, and multiplexers. Additionally, we needed an FSM (finite state machine) to control these building blocks. In this article, we’ll look at the details of designing the FSM. Then, we’ll write the Verilog code for the different blocks and use the Mojo V3 board to verify our design.”