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Simulating Verilog designs on a microcontroller

What does it do?
This project aims to simulate Verilog HDL designs on a Raspberry Pi Pico (or any other RP2040-based board). It achieves this by using Verilator to compile the RTL into a cycle-accurate C++ model of your design which can then be executed on the microcontroller. This allows you to access the signals of the simulated design through the GPIO pins of the board, which gives a more hands-on experience than simulating on a computer. It is many orders of magnitude slower than a real FPGA (max clock speed is 5kHz, and it goes down as the complexity of your design increases), but it can still be used as an educational tool. In terms of user experience, it feels like using a slower FPGA (at least for simpler designs), hence the name of the project: FakePGA.”

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