WoW! TSMC Sticks Whole Wafers Together

Today it is the TSMC Technology Symposium. As always, Cadence is making several announcements jointly with TSMC.

5nm and 7nm+
This isn’t the biggest surprise announcement of the year. Cadence is collaborating with TSMC on 5nm and 7nm+ high-performance processes primarily targeted at advanced mobile and high-performance computing (HPC). There is certification of the digital and signoff flow, the custom/analog flow, and the library characterization flow. There is a press release, but you can pretty much take last year’s, or the year before’s, and just lower the numbers. The entire Cadence tool portfolio supports the entire TSMC process portfolio. TSMC has said (and I’m assuming they will re-iterate in the tech symposium today) that 5nm is on-track for Q1 2019. They also announced last year that they will build the world’s first 3nm fab in Tainan, so you can get ahead and write your own future press release.

WoW Advanced Packaging Technology
If you do as I did, and google “wow packaging” then the first hit is a Pinterest page showing 40 amazing packages: for sandwiches, wine, pasta, and even The Beatles White Album. But no chips, not even the kind made from potatoes. WoW stands for Wafer-on-Wafer and is the name for TSMC’s 3D stacking technology. For chips of the silicon kind of course. This is a third 3D technology, to join the two existing TSMC packaging technologies CoWoS and InFO (which respectively stand for chip-on-wafer-on-substrate and integrated-fan-out).

wafer on waferWafer-on-wafer involves two wafers. The upper wafer is flipped over onto the lower. Obviously, the pads on the two wafers need to be mirror images of each other so that they align. The two wafers are then joined, bonding layer to bonding layer. It is part of the secret-sauce how TSMC makes that work.

Of course, that immediately creates a problem: how do you get the signals out given that the two wafers only have their backs exposed. The answer is that the one wafer has thru-silicon-vias (TSVs) for the I/Os. The naming is actually very confusing, since what I called the upper wafer, as in the one on top in the picture to the right, is conventionally called the “bottom” wafer, since it will be packaged using flip-chip technology, and so top and bottom are switched in the flip. So it is the top wafer that has the TSVs (which is then flipped) and appears on the bottom in the picture to the above right. Then the die are separated by sharks with laser beams…or diamond saws, which sounds almost as good.

By the way, I do know that technically the plural of die is dice. But to anyone in the industry, the word “die” conjures up chips, and “dice” conjures up craps. So I just use “die” as if it is both singular and plural. Like “cod”. Two cod are still cod.

Obviously, since this is working at the wafer level, the so-called “known good die” problem is aggravated. Even if a die is known to be bad from wafer sort, it is still going to get bonded to a (probably) good die on the other wafer, which will eventually get discarded. So yields need to be high enough to make the savings from working at the wafer level cover the fact that some good die are going to be sacrificed.

Furthermore, the packaging technologies can be combined, using WoW to join wafers, and then putting them on an interposer, creating a 2-die cube. In fact, it is possible to vertically stack more than two wafers if all except the very bottom one (the one that ends up on top…yes, your head does hurt) have TSVs to get the signals between the layers.

Cadence already supports TSMC’s earlier 3D technologies CoWoS and InFO (your little fingers get a workout on the shift keys typing these packaging names). There are multiple designs in production. WoW expands on this with support for 3D stacking with larger die sizes and denser I/O pins. What Cadence and TSMC announced today is that the Cadence flows are certified for TSMC’s WoW Reference Flow 1.0.”

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