Content for Digilent Arty Z7

Digilent Arty Z7

The Arty Z7 is a ready-to-use development platform designed around the Zynq-7000™ All Programmable System-on-Chip (AP SoC) from Xilinx. The Zynq-7000 architecture tightly integrates a dual-core, 650 MHz ARM Cortex-A9 processor with Xilinx 7-series Field Programmable Gate Array (FPGA) logic. This pairing grants the ability to surround a powerful processor with a unique set of software defined peripherals and controllers, tailored by you for whatever application is being conquered. The design process is very straightforward and provides a systematic path between defining your custom peripheral set and bringing it's functionality up to a Linux OS running on the processor. Digilent provides a number of materials and resources for the Arty Z7 that will get you up and running with this process quickly.

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Project  Measuring Circuit Delay for FPGA Timing using the ADP3450

Measuring Circuit Delay for FPGA Timing using the ADP3450

“Using the ADP3450, this project measures amount of delay between asserting FPGA IO on base of NPN 2N3094 and LED illuminating on collector. Signal timing is a huge component in FPGA design, and while many tutorials demonstrate how to handle …

Project  Introduction to Using AXI DMA in Embedded Linux

Introduction to Using AXI DMA in Embedded Linux

“This tutorial walks through an application that reads/writes data to DDR memory from the Linux userspace on the Zynq-based Arty Z7 FPGA. Story Direct memory access, or DMA as it’s referred to, is an important aspect of embedded …

Project  Getting Started with the Arty Z7 in Vivado 2020.2

Getting Started with the Arty Z7 in Vivado 2020.2

“See how to build a base hardware image for the Arty Z7 FPGA development board in Vivado 2020.2 Story In this project, I will walk through the steps of setting up a basic hardware design in Vivado for the …

Project  DSP for FPGA: Using Xilinx DDS with Custom FIR

DSP for FPGA: Using Xilinx DDS with Custom FIR

“See how to integrate your custom FIR with Xilinx DSP IP such as their DDS Compiler IP. Continuing with my series of a practical example of implementing a simple FIR in custom RTL, my next step is to use my …

Project  DSP for FPGA: Rewriting FIR Logic to Meet Timing

DSP for FPGA: Rewriting FIR Logic to Meet Timing

“Continuing with my simple FIR filter Verilog module, this project walks through how to rewrite HDL logic when setup timing violations occur. In my last project, I demonstrated the initial steps to writing a custom FIR module in Verilog. That …

Project  Big. LITTLE (ish) with DesignStart FPGA and Zynq at the Edge

Big. LITTLE (ish) with DesignStart FPGA and Zynq at the Edge

“How to integrate DesignStart Arm Cortex-M1 and M3 processors with the Xilinx Zynq. Introduction Several times this year I have presented courses in person or online about how to implement the Arm DesignStart FPGA cores in Xilinx FPGAs. I have …