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DSP for FPGA: Using Xilinx DDS with Custom FIR

See how to integrate your custom FIR with Xilinx DSP IP such as their DDS Compiler IP.

Continuing with my series of a practical example of implementing a simple FIR in custom RTL, my next step is to use my custom FIR RTL with Xilinx’s DDS Compiler IP block, which will exercise the FIR in a way that any practical application in a larger project might.

To fully validate my custom FIR Verilog module, I decided that using the DDS Compiler IP block to output a chirp signal that starts in the passband of my FIR (which currently contains coefficients for a low pass filter with a sample rate of 100Mbps) and increases until it ends in the FIR’s stopband.”

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