With increase in size of FPGA, the complexity of design implemented on FPGA is also increasing. In often cases, the design works fine on simulation but behaves differently on hardware. So, there arises a need to debug/monitor buses/signals on FPGA. This task is primarily accomplished by using state-of-the-art logic analyzer IP provided by FPGA vendor e.g. The SignalTap® II Embedded Logic Analyzer (ELA) from Altera and The Integrated Logic Analyzer (ILA) from Xilinx. Both are system-level debugging tool that captures and displays real-time signals in a FPGA design. By using logic analyzer in systems, designers can observe the behavior of hardware (such as peripheral registers, memory buses, and other on-chip components) in response to software execution. However, these logic analyzers present some major challenges. The two most important drawbacks of using such logic analyzers are – (1) the amount of data that can be captured is limited by the amount of memory blocks available on a FPGA device; (2) with increase in the capture depth, the area occupied by the logic analyzer IP also increases. These drawbacks pose a major obstacle in debugging. This project attempts to address this issue.
The purpose of this project was to build a system which can be used to debug real-time signals in a FPGA design by capturing and visualizing the signals in real-time on VGA Monitor. The system also has a USB mouse interface which is used to zoom in/out of the display and to scroll through the waveform. The system implemented in this project can capture and display 32 bit signals probed in FPGA on 640x480 VGA Monitor in real-time. Figure 2 shows the setup for this lab. The project demo was performed using Terasic DE1-SoC development kit built around the Altera System-on-Chip (SoC) FPGA combining dual-core Cortex A9 (HPS) with programmable fabric.”