Content for RISC-V

RISC-V

RISC-V (pronounced "risk-five") is an open-source hardware instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. Unlike other academic designs which are optimized only for simplicity of exposition, the designers state that the RISC-V instruction set is for practical computers. It is said to have features to increase computer speed, yet reduce cost and power use. These include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, simplified standards-based floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. Sign extension is said to often be on the critical timing path.

Alibaba Cloud Unveils New Server Chips to Optimize Cloud Computing Services

“Alibaba Cloud, the digital technology and intelligence backbone of Alibaba Group, today unveiled a new in-house processor design for use in its data centers. The server chips, named Yitian 710, are custom-built by Alibaba Group’s chip development business, T-Head …

First RISC-V computer chip lands at the European Processor Initiative

“The European Processor Initiative (EPI) has run the successful first test of its RISC-V-based European Processor Accelerator (EPAC), touting it as the initial step towards homegrown supercomputing hardware. EPI, launched back in 2018, aims to increase the independence of …

Creating a RISC-V system with an FPGA

“In this project you will learn how to implement a RISC-V processor in a SmartFusion2 SoC. Everybody knows that the processor of the moment is the RISC-V, even it is not a processor itself, the amount of the …

RISC-V Launches the Open Hardware Diversity Alliance

” RISC-V International, a global open hardware standards organization, today announced the launch of the Open Hardware Diversity Alliance. The global Alliance, created by CHIPS Alliance, OpenPOWER Foundation, RISC-V, and Western Digital, will develop and provide learning and networking …

The NEORV32 RISC-V Processor

“The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based on the RISC-V NEORV32 CPU. The project is intended as auxiliary processor in larger SoC designs or as ready-to-go stand-alone custom / customizable microcontroller.”

MIPS Technologies joins RISC-V, moves to open-source ISA standard

“The MIPS silicon manufacturer is one of the oldest RISC chip manufacturers, used in several systems since the late 80s. Characterized by clean and efficient designs, allowing adaption in varied applications, this company has been considered one of the most …

BeagleBoard.org® and Seeed Introduce the First Affordable RISC-V Board Designed to Run Linux

“Seeed and BeagleBoard.org® have announced an official collaboration with the leading RISC-V solutions provider, StarFive, to create the latest member of the BeagleBoard.org® series, BeagleV™ (pronounced Beagle five.) BeagleV™ is the first affordable RISC-V board designed …

Andes RISC-V Vector Processor NX27V is Upgraded to RVV 1.0

“Andes Technology Corporation, a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, today announces the first commercial RISC-V vector processor IP, AndesCore™ NX27V, is upgraded to support …

Programming the GD32V Longan Nano

“RISC-V is gaining traction and some development boards have already popped up. One of them is the widely available Sipeed Longan Nano. Written information is a bit sparse at the moment. Let’s try to fix this with a …

RISC-V, the Linux of the chip world, is starting to produce technological breakthroughs

“A decade ago, an idea was born in a laboratory at the University of California at Berkeley to create a lingua franca for computer chips, a set of instructions that would be used by all chipmakers and owned by none …

PULPino An open-source microcontroller system based on RISC-V

“PULPino is an open-source microcontroller system, based on a small 32-bit RISC-V core developed at ETH Zurich. The core has an IPC close to 1, full support for the base integer instruction set (RV32I), compressed instructions (RV32C) and partial …