“Digital clock (time) on 4 single 7 segment common anode display implemented hardware on Xilinx Spartan 6 FPGA.
Digital clock (time watch) on 4 single 7 segment common anode display implemented hardware on Xilinx Spartan 6 FPGA. Use.ucf (implementation constrains) file to assign user IO ports of FPGA to Inputs & Outputs of.vhd (VHDL) file.”