“Toshiba Electronic Devices & Storage Corporation (“Toshiba”) and its manufacturing subsidiary, Japan Semiconductor Corporation, have developed technology to improve the reliability of P-channel Laterally Double Diffused MOS (Pch-LDMOS) technology for analog ICs. The companies clarified the cause of degradation of breakdown voltage that occurs in the drain avalanche hot-carrier (DAHC) stress test, a reliability test for LDMOS, and identified a device structure that suppresses the degradation.
Details were reported at the IEEE-sponsored International Symposium on Power Semiconductor Devices and ICs 2020 (ISPSD 2020) held online.
The electrification of vehicles and automation of industrial equipment is stimulating demand for analog ICs that can maintain high reliability over the long term in low- and high-temperature environments. This has drawn increasing interest in LDMOS, which has low on-resistance that makes it suitable for a wide range of application.
In the drain avalanche hot-carrier (DAHC) stress test, LDMOS reliability is evaluated by applying a medium voltage to its gate over a long period. The test measures degradation of breakdown voltage, a known cause of damage and reduced reliability in analog ICs.
Until now, the mechanism that causes the degradation in breakdown voltage was not clear, but widely assumed to be due to a trapped charge in the corner of the shallow trench isolation (STI), where the impact-ionization rate is the highest. The two companies’ investigation of electron flow and device structure found that the cause was different, a trapped charge in the bottom STI, not the corner.
The companies found that the RESURF structure is more tolerant of breakdown voltage degradation than the more commonly used DRIFT structure, because an additional junction underneath the drift region shares balances the total electric field across the region. The RESURF structure suppresses degradation to two-thirds that of the DRIFT structure.”