“Engineers can design high-speed digital control loops with the highest dynamic range and lowest latency while reducing power consumption by as much as 65%
Texas Instruments (TI) (Nasdaq: TXN) today expanded its portfolio of high-speed data converters with a broad new family of successive-approximation register (SAR) analog-to-digital converters (ADCs) that enable high-precision data acquisition in industrial designs. Featuring best-in-class dynamic range at the lowest power consumption, the ADC3660 family includes eight SAR ADCs in 14-, 16- and 18-bit resolution at sampling speeds ranging from 10 to 125 MSPS, helping designers improve signal resolution, extend battery life and strengthen system protection. For more information, explore the ADC3660 family at www.ti.com/ADC3660family-pr.
Increasing the precision of high-speed data acquisition addresses a rising need for real-time control in industrial systems. In a high-speed digital control loop, the ADC acts in a complex system to respond to fast changes in voltage or current to help prevent costly damage to critical components in power-management systems. As the number of data-intensive tasks in industrial systems increases, it becomes more important for the system to make quick decisions to prevent system failure, requiring higher precision at faster speeds.
Protect industrial systems with faster response times in digital control loops
The ADC3660 family delivers up to 80% lower latency than competitive devices at similar speeds. For example, system designers can achieve one-clock (8 ns) ADC latency with the 125-MSPS, 14-bit, dual-channel ADC3664. The family’s ultra-low latency enables high-speed digital control loops in a wide variety of industrial systems to more accurately monitor and respond to voltage and current spikes, increasing tool precision in applications such as semiconductor manufacturing systems.
Get industry-leading noise performance at the lowest power consumption
Up until now, engineers designing industrial systems had to choose between excellent noise performance and low power consumption – an especially difficult decision for those designing battery-operated devices that require precise data acquisition. The ADC3660 family eliminates this trade-off. For example, the ADC3683 – the industry’s fastest 18-bit ADC at 65 MSPS – improves noise performance in narrowband-frequency applications such as portable defense radios, offering a signal-to-noise ratio (SNR) of 84.2 dB and a noise spectral density of -160 dBFS/Hz while maintaining low power consumption of 94 mW per channel. Consuming 36 mW total, the 10-MSPS, 14-bit ADC3541 simplifies thermal management and extends battery life in power-sensitive applications such as GPS receivers or handheld electronics. And the 65-MSPS, 16-bit ADC3660 delivers 82 dBFS SNR, improving image resolution in sonar applications while consuming 65% less power (71 mW per channel) than the equivalent competitive device. Watch the video, “Increasing signal detection capability in industrial applications,” to learn more about how the family’s noise performance contributes to higher accuracy and better image resolution.
Reduce design complexity with integrated features and high sampling frequencies
The ADC3660 family’s high sampling speeds and integrated features help designers reduce the number of components in their systems. For example, the ADC3683 – which samples four times faster than the closest competing 18-bit device at twice the channel density – enables oversampling, a technique that pushes harmonics further from the desired signal. This allows designers to reduce antialiasing filter complexity and system component count by as much as 75%.
Other family features that reduce design complexity include on-chip decimation options that enable designers to easily remove unwanted noise and harmonics in the system and boost SNR and spurious-free dynamic range up to 15 dB. These decimation options, along with the complementary metal-oxide semiconductor (CMOS) interface, enable designers to use these ADCs with Arm®-based processors or digital signal processors instead of field-programmable gate arrays (FPGAs), which can help lower system cost.
Additionally, an integrated digital downconverter with a complex numerically controlled oscillator reduces the amount of processor resources required. To learn more, read the Analog Design Journal article, “How to simplify AFE filtering via high-speed ADCs with internal digital filters.”“