“PCI-SIG Developers Conference 2017 - PCI-SIG®, the organization responsible for the widely adopted PCI Express® (PCIe®) industry-standard input/output (I/O) technology, today announced the release of the PCI Express 4.0, Revision 0.9 Specification, supporting 16GT/s data rates, flexible lane width configurations and speeds for high-performance, low-power applications. The ubiquitous PCIe I/O architecture continues to outpace other interconnect technologies in terms of market share, capacity and bandwidth – doubling per-pin bandwidth while maintaining full backwards compatibility. “I’m pleased to say that the PCIe 4.0 specification is feature complete and going through final IP review,” said Al Yanes, PCI-SIG Chairman and President. “We extended the original timeline to adhere to our meticulous specification review process that has made PCIe technology so successful. We are confident that the PCIe architecture is sound for the foreseeable future and ready for the next generation of high-performance bandwidth.” Originating as the cornerstone for I/O connectivity in personal computing, the PCIe architecture has become the interconnect of choice for the expansive server and storage market. More recently, the PCIe architecture has also evolved into the backbone for the proliferating cloud ecosystem and served as the I/O attach point in mobile, IoT, networking and external I/O connectors. The PCIe 4.0 architecture is poised to continue its evolution in delivering power-efficient performance. New functional enhancements include, extended tags and credits for service devices, reduced system latency, lane margining, superior RAS capabilities, scalability for added lanes and bandwidth, as well as improved I/O virtualization and platform integration.”