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“An AVR, 128MB SDRAM DIMM, old laptop LCD, and a handful of TTL chips — 30+MS/s 32-channel logic-analyzer interface for an analog ‘scope. This is a Sample/Repeat “Logic Analyzer” with up to 32 channels at 30+MS/s …
Content for MT48LC8M8A2
The 64Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 67,108,864 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x8’s 16,777,216-bit banks is organized as 4096 rows by 512 columns by 8 bits. Each of the x16’s 16,777,216-bit banks is organized as 4096 rows by 256 columns by 16 bits.