“Toshiba Corporation (TOKYO: 6502) today unveiled the latest generation of its BiCS FLASHTM three-dimensional (3D) flash memory with a stacked cell structure1, a 64-layer device that will be first2 in the world to start sample shipments today. The new device incorporates 3-bit-per-cell (triple-level cell, TLC) technology and achieves a 256-gigabit (32gigabytes) capacity, an advance that underscores the potential of Toshiba’s proprietary architecture. Toshiba continues to refine BiCS FLASHTM, and the next milestone on the development roadmap is a 512-gigabit (64-gigabytes) device, also with 64 layers. The new device succeeds the 48-layer BiCS FLASHTM, and its leading-edge 64-layer stacking process realizes a 40% larger capacity per unit chip size than 48-layer stacking process, reduces the cost per bit, and increases the manufacturability of memory capacity per one silicon wafer. 64-layer BiCS FLASHTM can meet demanding performance specs, and the new device will be used in applications that include enterprise and consumer SSD, smartphones, tablets and memory cards.”
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